Metal silicides formed on polysilicon, or “polysilicon metal silicides” are widely used in semiconductor industry for their conductivity, which is higher than the conductivity of a doped polysilicon. The conductivity of a polysilicon metal silicide is about two orders of magnitude greater than the conductivity of even the most heavily doped polysilicon, thus polysilicon metal silicides provide a relatively low resistance wiring. A polysilicon metal silicide with a thickness of about 25 nm has a sheet resistance on the order of 10 Ohms per square.
A most typical application of polysilicon metal silicides is a gate metal silicide. A MOSFET comprises a gate which contains a gate dielectric and a gate conductor. After the formation of the gate dielectric, a polysilicon layer is deposited and patterned to define the gate. After formation of gate spacers, a metal layer is deposited over and reacted with the underlying polysilicon layer. Polysilicon in an upper portion of the polysilicon layer reacts with the metal layer and forms a gate metal silicide, which is a polysilicon metal silicide.
Utilizing the conductive property of polysilicon metal silicides, polysilicon metal silicide wiring is extensively used in semiconductor applications to provide an electrical connection between adjacent semiconductor devices on a gate conductor level, or as commonly referred to, on a “polysilicon conductor” (PC) level. The gate of a MOSFET, which comprises a stack of a polysilicon layer and a gate metal silicide layer, is extended over shallow trench isolation that surrounds the MOSFET and is connected to a portion of another device, such as the gate of another MOSFET. For example, a CMOS inverter has a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) in a series connection such that the drains of the PFET and NFET are electrically connected and the gates of the PFET and the NFET are electrically connected. Polysilicon metal wiring is used in this case to connect the gate of the PFET and the gate of the NFET. Such wiring on a PC level may be practiced on any adjacent MOSFET devices or even on bipolar devices provided that suitable polysilicon metal silicides are present.
Polysilicon metal silicide wiring according to the prior art utilizes P+ doped polysilicon or N+ doped polysilicon to form polysilicon metal silicides. Due to the presence of dopants in the polysilicon, the silicides tend to be more prone to defects in the subsequently formed polysilicon metal silicides compared to polysilicon metal silicides formed from an undoped polysilicon.
Referring to FIGS. 1A and 1B, an exemplary polysilicon metal silicide wiring structure according to the prior art is shown. FIG. 1A is a top-down view and FIG. 1B is a vertical cross-sectional view of along the plane B-B′ in FIG. 1A. Two p-type MOSFETs and two n-type MOSFETs are shown on a semiconductor substrate 110. Each of the two p-type MOSFETs comprises P+ doped source and drain regions 161, a gate dielectric 130, a block of P+ doped polysilicon 131 and a block of P+ doped polysilicon metal silicide 141. Each of the two n-type MOSFETs comprises N+ doped source and drain regions 162, a gate dielectric 130, a block of N+ doped polysilicon 132, and a block of N+ doped polysilicon metal silicide 142. The block of P+ doped polysilicon 131, the block of P+ doped polysilicon metal silicide 141, the block of N+ doped polysilicon 132, and the block of N+ doped polysilicon metal silicide 142 collectively form a gate line. Connections between adjacent MOSFETs are formed by extensions of the gate conductor that may be a stack of the Block of P+ doped polysilicon 131 and the block of P+ doped polysilicon metal silicide 141, a stack of the block of N+ doped polysilicon 132 and the block of N+ doped polysilicon metal silicide 142, or a combination thereof.
To form the Block of P+ doped polysilicon 131 and the block of N+ doped polysilicon 132, an undoped polysilicon layer may be deposited over the gate dielectric layer 130 and over a shallow trench isolation 120, lithographically patterned, and etched. Implantation of p-type dopants with a first mask and implantation of n-type dopants with a second mask follow. The first mask allows the p-type dopants into a “p-type implant area” 151 that includes the STI area that surrounds the PFETs, while blocking the p-type dopants outside the p-type implant area 151. The second mask allows the n-type dopants into an “n-type implant area” 152 that includes the STI area that surrounds the NFETs, while blocking the n-type dopants outside the n-type implant area 152.
Neighboring active areas containing the same type of MOSFET belong to the same p-type implant area. Therefore, an STI area located between two neighboring PFETs or two neighboring NFETs belongs to the same implant area as the two neighboring MOSFETs. Most often, an edge of the p-type implant area 151 contacts an edge of the n-type implant area 152 within an overlay tolerance of lithography used to define the two implant areas (151, 152). An STI area located between a PFET and a neighboring NFET is split into two portions, in which a first portion belongs to a p-type implant area 151 and a second portion belongs to an n-type implant area 152 and the two implant areas adjoin each other. If one of the species of the dopants have a faster diffusion rate within polysilicon, the boundary between the block of P+ doped polysilicon 131 and the block of N+ doped polysilicon 132 may move into the polysilicon region with slower dopant diffusion speed. This is exemplified in FIG. 1A for a case wherein the p-type dopants have a higher diffusion rate than the n-type dopants. Alternately, a heavily doped polysilicon layer, instead of an undoped polysilicon layer, may be deposited over the gate dielectric layer and patterned followed by an implantation of the dopants of the opposite type in sufficient quantity to reverse the doping type on a portion of the heavily doped polysilicon layer. Both methods produce two types of heavily doped polysilicon layers that adjoin each other in some locations.
Typically, spacers (not shown) are formed around the heavily doped polysilicon layers. A metal layer comprising a silicide forming metal, for example cobalt, tantalum, titanium, nickel, other refractory metal or an alloy thereof, is subsequently deposited and reacted to form silicides. The reacted metal layer forms a metal silicide (not shown) on the P+ doped or N+ doped source and drain regions (161, 162). The reacted metal layer also forms a block of P+ doped polysilicon metal silicide 141 on top of the block of P+ doped polysilicon 131 and a block of N+ doped polysilicon metal silicide 142 on top of the block of N+ doped polysilicon 132. The properties of the P+ doped polysilicon metal silicide and the properties of the N+ doped polysilicon metal silicide are different from the properties of an undoped polysilicon metal silicide, that is, a metal silicide material by reacting a metal with an undoped polysilicon, in that the presence of the p-type or n-type dopants in high concentration (on the order of about 1 atomic percent) impedes the silicidation process, making the resulting doped polysilicon metal silicide more prone to defects than an undoped polysilicon metal silicide.
The exemplary polysilicon metal silicide wiring structure according to the prior art in FIGS. 1A and 1B comprises a block of P+ doped polysilicon, a block of N+ doped polysilicon adjoining the P+ polysilicon, a block of P+ doped polysilicon metal silicide adjoining the block of P+ doped polysilicon, and a block of N+ doped polysilicon metal silicide adjoining the block of N+ doped polysilicon and adjoining the block of P+ doped polysilicon metal silicide.
While the resistivity of a metal silicide is typically about two orders of magnitude lower than the resistivity of a heavily doped polysilicon, the resistance per unit width and length of gate wiring of P+ doped polysilicon or N+ doped polysilicon is only about one order of magnitude higher than the resistance per unit width and length of gate wiring of a polysilicon metal silicide since the thickness of a typical doped polysilicon layer is about one order of magnitude greater than the thickness of a typical polysilicon metal silicide.
According to the prior art, a defect such as a break in a polysilicon metal silicide wiring, is not easily detectable since the loss in conductance of the wiring due to the defect in the polysilicon metal silicide is partly compensated for by the P+ doped polysilicon or N+ doped polysilicon that provides a parallel electrical conduction path to the defect in the polysilicon metal silicide. The overall increase in the resistance of the wiring may not be significant and therefore, may not be easily detectable in a low-speed test, in which DC condition must lead to a detectable product failure, i.e., product test conditions that apply virtually constant voltage or current signals, are performed. However, MOSFET devices typically operate at a high frequency, e.g., at a frequency over 1 GHz, and the functionality of the MOSFET devices rapidly deteriorate due to presence of such defects in the polysilicon metal silicide wiring. In other words, while the defects in the polysilicon metal silicide wiring is not easily detectable in a low-speed test, the same defects in the polysilicon metal wiring cause significant circuit degradation in the circuit performance.
Testing of the individual MOSFET devices for circuit performance to guard against the possibility of circuit degradation due to defects in the polysilicon metal wiring requires a high-speed functional tester, in which AC measurements, i.e., measurements that apply high frequency signals, are performed. High-speed functional testing tends to be costly and time-consuming.
Therefore, there exists a need for a semiconductor structure that reduces the defect density in a polysilicon metal silicide wiring.
Furthermore, there exists a need for a semiconductor structure that allows a less costly detection of presence of defects in a polysilicon metal silicide wiring, and preferably in a low-speed testing.